The use of quartz substrates in a microelectromechanical systems (MEMS) process provides for the fabrication of high quality (Q) factor and thermally compensated resonators. For thickness shear mode resonators, the thickness of the substrate determines the resonant frequency of the resonator. The thinner the quartz substrate, the higher the resonant frequency. Therefore, by varying the thickness of the substrate over a broad range, the resonant frequency can be adjusted over a broad range. Having a quartz substrate with a thickness on the order of 10 microns or less can result in resonant frequencies greater than 100 MHz, which is desirable for high frequency applications.
By combining several quartz based resonators having different resonant frequencies with a radiofrequency (RF) MEMS switch on the same chip, frequency hopping and filter reconfiguration can occur on the microsecond time scale. In frequency hopping and filter reconfiguration the desired frequency in a band of frequencies is selected by using the RF MEMS switch to activate the quartz resonator having a resonant frequency equal to the desired frequency. The spectral band for most radio frequency hopping and filter reconfiguration applications is 20 MHz to 3 GHz. The low frequency part of the band is extremely difficult to cover with conventional capacitive-based filters since capacitive-based filters are larger in size. Frequency hopping and filter reconfiguration applications would benefit from temperature compensated, stable, high-Q (in the amount of about 10,000), arrays of resonators and filters.
However, present quartz fabrication techniques for oscillators or filters do not allow quartz resonators to be integrated on a chip with other electronics. The inability to integrate the quartz resonators on a chip with other electronics is a significant contributing factor to the size and cost of a device due to the need to use separate off-chip components.
MEMS devices which consist of silicon-based nanoresonators have been fabricated in an attempt to integrate nanoresonators or microresonators with other electronics. Nanoresonators and microresonators are resonators which have linear dimensions on the order of nanometers and micrometres or microns, respectively. These silicon-based nanoresonators have shown resonant frequencies as high as 1 GHz, and quality factors in the range of 1000-2000. However, the problem with silicon-based nanoresonators is that they have high electrical impedances and high temperature drift.
An alternative solution is known which makes use of non-MEMS quartz resonators. Such resonators usually consist of shear strip individual resonators operating in ranges of about 10 MHz to about 250 MHz. These resonators are packaged as discrete devices and mounted as hybrids to other RF circuits. The problem with non-MEMS quartz resonators is that they are non-integrable, they have higher costs, lower frequencies, and they are physically larger in size.
U.S. patent application Ser. No. 11/426,931 for “Quartz-Based Nanoresonators and Method of Fabricating Same,” published as 2004/0211052 A1, is co-owned with and a parent to the current application. The disclosure of U.S. patent application publication 2004/0211052 is hereby incorporated by reference in this specification for all purposes allowed by law and regulation. This application is addressed to a method for fabricating a quartz nanoresonator that can be integrated on a substrate along with other electronics. It teaches a method for fabricating and integrating quartz-based resonators on a high speed substrate for integrated signal processing that utilizes a combination of novel bonding and etching steps to form ultra thin quartz based resonators. Thinning the quartz substrate in the quartz resonator provided the desired resonant frequency. The quartz resonators made by this process may achieve a frequency in excess of 1 GHz.
The first embodiment of the process for forming quartz nanoresonators disclosed in U.S. patent application publication 2004/0211052 is shown in general outline in the diagrams of FIGS. 1-13 of that patent application publication. Referring now to the drawings of the present specification, FIGS. 1-8 summarize this process. The step shown in FIG. 1 shows the provision of the starting materials, namely, wafers or substrates of single-crystal quartz 2 and silicon 4 (the “silicon handle”). The quartz wafer 2 has a first surface 3 and a second surface 5.
The next step is shown in FIG. 2, which is to define and etch a cavity 7 in the silicon handle wafer 4. A third step, shown in FIG. 3, is to deposit the top-side electrode 10 and the interconnect bond metal 8 metal onto the quartz wafer 2 using known methods of patterning and metalizing. The electrode 10 is a “top-side” electrode because ultimately first surface 3 will be the top surface and the electrode 10 will be on top.
In a fourth step, shown in FIG. 4, the quartz wafer 2 is reversed and then brought together with the silicon handle wafer 4 using a direct bonding process.
A fifth step, shown in FIG. 5, uses lapping and reactive ion etching to thin and polish at least part of the quartz wafer 2 into a to a precisely measured thickness suitable for the desired resonant frequency. It will be appreciated that second surface 5 is now closer to first surface 3 due to the thinning of the quart wafer 2. Next, in a sixth step, shown in FIG. 6, photolithography techniques are used to pattern and metallize via holes 12 in the quartz wafer. In a seventh step, shown in FIG. 7. bottom-side bonding pads 14, and bottom side electrode 16, are deposited.
The contact vias 12 will provide electrical access to the top-side electrodes of the resonator from the bottom-side bonding pads 14 that will be in contact with probe pads on the substrate or host wafer 6 that will support the quartz resonator. The host wafer 6 could contain high-speed RF electronics, thus eliminating the need for lengthy bond wires and facilitating on-chip integration.
In an eighth step, see FIG. 8, the quartz wafer 2 is patterned and etched into a modified quartz substrate 2a, thus forming the final resonator 20. The resonator 20 is still attached to the silicon handle 4.
In a later step shown in U.S. patent application publication 2004/0211052, but not shown in the drawings of this application, the quartz resonator is later transferred and attached to a base substrate of about the same diameter. Since quartz wafers are typically grown in sizes up to four to five inches (10.2 to 12.7 centimeters), bonding a four inch quartz wafer to a twelve inch (30.5 centimeters) CMOS wafer would not utilize all the electronic components on the CMOS wafer. One would prefer to bond a twelve inch quartz wafer to a twelve inch CMOS wafer but twelve inch quartz wafers are not available. FIGS. 10 and 11 of U.S. patent application publication 2004/0211052 show the shaping and addition of probe pads to the base substrate and FIG. 12 of that publication shows the attachment of the quartz resonator to the probe pads on the base substrate. In a still later step (shown in FIG. 13 of U.S. patent application publication 2004/0211052) the silicon handle wafer 4 is removed from the quartz resonators 20.
The purpose of the first and second bonding metals 8 and 14 is to receive an electrical signal from the probe pads which can bias or drive the resonator 20 with an electric field. The electrical signal is preferably an AC signal. When the electrical signal is received by the first and second electrodes 10 and 16 a stress is placed on the modified quartz substrate 2a. This stress stimulates the mechanical resonant frequency of the modified quartz substrate 2a by the piezoelectric effect, thereby causing the modified quartz substrate 2a to oscillate at its resonant frequency. Additionally, it is also possible to use the first and second electrodes 10 and 16 to sense the movement of the modified quartz substrate 2a relative to a specified plane (not shown). Once the modified quartz substrate 2a is oscillating at its resonant frequency, it can be used to drive other electrical components at a frequency equal to its resonant frequency. a 8 and testable. By ablating a portion of the bottom electrode 16, the resonant frequency of the quartz resonator 20 can be adjusted before final integration with the CMOS substrate. This ablation can be performed with known techniques such as focussed ion beam milling or laser ablation. finally, the wafer is diced for final assembly onto the electronic substrate.
U.S. patent application publication 2004/0211052 addressed direct wafer-to-wafer bonding of quartz devices to electronics and was only applicable to electronics wafers with diameters of about four inches or less. Since there is low demand for large quartz wafers, wafers of crystalline quartz larger than about four to five inches in diameter are not available. In addition, the packaging density of the quartz resonators on the final CMOS wafer will not in general provide for optimal useage of the quartz wafer and can result in wasted quartz.
Present quartz fabrication techniques for oscillators or filters do not allow the resonators to be integrated on-chip with associated electronics. Only individual oscillators can be purchased for hybrid integration with RF circuits for wireless applications. U.S. patent application 2004/0211052 describes a process to integrate the quartz devices on electronic substrates, but only for wafers which are four to five inches in diameter. This limits the large volume production on CMOS wafers since most high voltage CMOS fabrication is performed on larger wafers. Only compound semiconductor processing of Group III-V electronics is currently being manufactured with four inch wafers. Precise wafer-to-wafer bonding can only be performed in current aligners with wafers of similar size. In addition, no solutions for integrating quartz devices or pre-testing and screening individual resonators for optimized yield were known.
As a result, a new process for integrating quartz-based resonators with electronics on a large area wafer is desired in order to solve the aforementioned problems.